A very common package for semiconductor devices is the leaded chip carrier. JEDEC, a semiconductor standards group, has established standard dimensions for plastic and ceramic dual-in-line packages (DIP's), plastic leaded chip carriers (PLCC's), and ceramic leaded chip carriers (CLCC's).
These packages all use "J" leads, which extend from a midpoint of the sides of the package and are bent downwardly around the package bottom edge and extend inward to form the bottom of the J. The curved bottom hereinafter is called the lead "tail".
It is the tail that is solder mounted to traces or conductive pads of a printed circuit board. A bent or misshapen tail will not make the proper contact with its trace. It is critical therefore that the tails of all leads in a package are substantially coplanar. The tails under current manufacturing processes are formed "blind" without anvils to help shape them. FIG. 1 shows a prior art typical package and J leads. Consequently if any of the leads are bent out of shape due to mishandling, they cannot be reformed easily.
The common current practice is to adjust the leads manually with pliers or tweezers. This is costly due to its slowness and also not very effective.